View LTC2946HDETRPBF_8519991.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc 2946 1 2946fa for more information www.linear.com/ltc2946 typical application features description wide range i 2 c power, charge and energy monitor the lt c ? 2946 is a rail - to - rail system monitor that measures current, voltage, power, charge and energy. it features an operating range of 2.7 v to 100 v and includes a shunt regu - lator for supplies above 100 v. the current measurement common mode range of 0 v to 100 v is independent of the input supply. a 12- bit adc measures load current, input voltage and an auxiliary external voltage. load current and internally calculated power are integrated over an external clock or crystal or internal oscillator time base for charge and energy. an accurate time base allows the ltc2946 to provide measurement accuracy of better than 0.6% for charge and 1% for power and energy. minimum and maximum values are stored and an overrange alert with programmable thresholds minimizes the need for software polling. data is reported via a standard i 2 c interface. the ltc2946 i 2 c interface includes separate data input and output pins for use with standard or opto-isolated i 2 c connections. the ltc2946-1 has an inverted data output for use with inverting opto-isolator configurations. wide range power, charge and energy monitor with onboard adc and i 2 c adc total unadjusted error (adin) applications n rail-to-rail input range: 0v to 100v n wide input supply range: 2.7v to 100v n shunt regulator for supplies >100v n ? adc with less than 0.4% total unadjusted error n 12- bit resolution for current and voltages n 1% accurate power and energy measurements n 0.6% accurate current and charge measurements n additional adc input monitors an external voltage n internal 5% or external time bases n continuous scan and snapshot modes n stores minimum and maximum values n alerts when limits exceeded n split sda pin eases opto-isolation n shutdown mode with i q < 40a n available in 4mm 3mm dfn and 16-lead msop packages n telecom infrastructure n industrial equipment n general purpose energy measurement l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. i 2 c interface nine i 2 c addresses accumulation enable optional crystal timebase sense + sense C gpio3 alert scl sdai sdao adin clkout gpio1 v dd intv cc adr1adr0 gnd gpio2 clkin ltc2946 measured voltage general purpose output toload 0.1f 0.02 v in 4v to 100v 2946 ta01a code 0 C0.10 adc tue (%) C0.05 0 0.05 0.10 1024 2048 3072 4096 2946 ta01b downloaded from: http:///
ltc 2946 2 2946fa for more information www.linear.com/ltc2946 pin configuration absolute maximum ratings v dd voltage .............................................. C0.3 v to 100 v sense + voltage ........................................... C1 v to 100 v sense C voltage ..... C1 v or sense + C 1v to sense + + 1v intv cc voltage ( note 3) ................... C0.3 v to lesser of 5.8 v, v dd + 0.3 v adr 1, adr 0, adin , sdao , sdao , gpio 1 to gpio 3 voltages ....................................................... C0.3 v to 7v clkout voltage ........................ C0.3 v to intv cc + 0.3 v clkin voltage ........................................... C0.3 v to 5.5 v intv cc clamp current ........................................... 35 ma (notes 1, 2) ltc2946 1615 14 13 12 11 10 9 17 gnd 12 3 4 5 6 7 8 sense + sense C adr1adin adr0 gnd clkout clkin v dd intv cc gpio1gpio2 gpio3 sdao sdai scl top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w, e pad gnd soldered down exposed pad (pin 17) is gnd, pcb gnd connection is op tional 12 3 4 5 6 7 8 v dd intv cc gpio1gpio2 gpio3 sdao sdai scl 1615 14 13 12 11 10 9 sense + sense C adr1adin adr0 gnd clkout clkin top view ms package 16-lead plastic msop t jmax = 125c, ja = 120c/w ltc2946-1 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 sense + sense C adr1adin adr0 gnd clkout clkin v dd intv cc gpio1gpio2 gpio3 sdao sdai scl top view de package 16-lead (4mm 3mm) plastic dfn 17 gnd t jmax = 125c, ja = 43c/w, e pad gnd soldered down exposed pad (pin 17) is gnd, pcb gnd connection is op tional 12 3 4 5 6 7 8 v dd intv cc gpio1gpio2 gpio3 sdao sdai scl 1615 14 13 12 11 10 9 sense + sense C adr1adin adr0 gnd clkout clkin top view ms package 16-lead plastic msop t jmax = 125c, ja = 120c/w scl , sdai voltages ( note 4) ..................... C0.3 v to 5.9 v scl , sdai clamp current ........................................ 5 ma operating temperature range ltc 2946 c ................................................ 0 c to 70 c ltc 2946 i ............................................. C40 c to 85 c ltc 2946 h .......................................... C40 c to 125 c ltc 2946 mp ...................................... C55 c to 125 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) ms package only .............................................. 300 c downloaded from: http:///
ltc 2946 3 2946fa for more information www.linear.com/ltc2946 order information electrical characteristics symbol parameter conditions min typ max units suppliesv dd v dd input supply voltage l 4 100 v v cc intv cc input supply voltage l 2.7 5.8 v i dd v dd supply current v dd = 48v, intv cc open shutdown l l 0.9 15 1.3 40 ma a i cc intv cc supply current intv cc = v dd = 5v shutdown l l 0.7 15 1.0 40 ma a v cc(ldo) intv cc linear regulator voltage 8v < v dd < 100v, i load = 0ma l 4.4 5 5.4 v v cc(ldo) intv cc linear regulator load regulation 8v < v dd < 100v, i load = 0ma to 10ma l 100 200 mv v ccz shunt regulator voltage at intv cc v dd = 48v, i cc = 1ma l 5.8 6.3 6.7 v v ccz shunt regulator load regulation v dd = 48v, i cc = 1ma to 35ma l 250 mv v cc(uvl) intv cc supply undervoltage lockout intv cc rising, v dd = intv cc l 2.3 2.6 2.69 v v dd(uvl) v dd supply undervoltage lockout v dd rising, intv cc open l 2.4 2.8 3 v v ddi2c(rst) v dd i 2 c logic reset v dd falling, intv cc open l 1.7 2.1 v v cci2c(rst) intv cc i 2 c logic reset intv cc falling, v dd = intv cc l 1.7 2.1 v sense inputsi sense + (hi) 48v sense + input current sense + , sense C , v dd = 48v shutdown l l 100 150 1 a a i sense C (hi) 48v sense C input current sense + , sense C , v dd = 48v shutdown l l 20 1 a a i sense + (lo) 0v sense + source current sense + , sense C = 0v, v dd = 48v shutdown l l C10 C1 a a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd is from 4v to 100v, unless otherwise noted. (note 2) lead free finish tape and reel part marking package description temperature range ltc2946cde#pbf ltc2946cde#trpbf 2946 16-lead (4mm 3mm) plastic dfn 0c to 70c ltc2946ide#pbf ltc2946ide#trpbf 2946 16-lead (4mm 3mm) plastic dfn C40c to 85c ltc2946hde#pbf ltc2946hde#trpbf 2946 16-lead (4mm 3mm) plastic dfn C40c to 125c ltc2946cde-1#pbf ltc2946cde-1#trpbf 29461 16-lead (4mm 3mm) plastic dfn 0c to 70c ltc2946ide-1#pbf ltc2946ide-1#trpbf 29461 16-lead (4mm 3mm) plastic dfn C40c to 85c ltc2946hde-1#pbf ltc2946hde-1#trpbf 29461 16-lead (4mm 3mm) plastic dfn C40c to 125c ltc2946cms#pbf ltc2946cms#trpbf 2946 16-lead plastic msop 0c to 70c ltc2946ims#pbf ltc2946ims#trpbf 2946 16-lead plastic msop C40c to 85c ltc2946hms#pbf ltc2946hms#trpbf 2946 16-lead plastic msop C40c to 125c ltc2946mpms#pbf ltc2946mpms#trpbf 2946 16-lead plastic msop C55c to 125c ltc2946cms-1#pbf ltc2946cms-1#trpbf 29461 16-lead plastic msop 0c to 70c ltc2946ims-1#pbf ltc2946ims-1#trpbf 29461 16-lead plastic msop C40c to 85c ltc2946hms-1#pbf ltc2946hms-1#trpbf 29461 16-lead plastic msop C40c to 125c ltc2946mpms-1#pbf ltc2946mpms-1#trpbf 29461 16-lead plastic msop C55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc 2946 4 2946fa for more information www.linear.com/ltc2946 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd is from 4v to 100v, unless otherwise noted. (note 2) symbol parameter conditions min typ max units i sense(lo) C 0v sense C source current sense + , sense C = 0v, v dd = 48v shutdown l l C5 C1 a a adc (sense + , sense ? = 0v, 100v) (note 5) res resolution (no missing codes) (note 7) l 12 bits tue total unadjusted error (note 6) sense (c-, i-grade) sense (h-, mp-grade) sense + , v dd (c-, i-grade) sense + , v dd (h-, mp-grade) adin (c-, i-grade) adin (h-, mp-grade) l l l l l l 0.6 0.7 0.4 0.5 0.3 0.4 % % % % % % v fs full-scale voltage sense (c-, i-grade) sense (h-, mp-grade) sense + , v dd (c-, i-grade) sense + , v dd (h-, mp-grade) adin (c-, i-grade) adin (h-, mp-grade) l l l l l l 101.8 101.7 102 101.9 2.042 2.04 102.4 102.4 102.4 102.4 2.048 2.048 103 103.1 102.8 102.9 2.054 2.056 mv mv v v v v lsb lsb step size sense sense + , v dd adin 25 25 0.5 v mv mv v os offset error sense (c-, i-grade) sense (h-, mp-grade) sense + , v dd adin l l l l 2.1 3.1 1.5 1.1 lsb lsb lsb lsb inl integral nonlinearity sense sense + , v dd adin l l l 2.5 2 2 lsb lsb lsb transition noise (note 7) sense sense + , v dd adin 1.2 0.3 10 v rms mv rms v rms t conv conversion time (snapshot mode) sense sense + , v dd , adin l l 62.4 31.2 65.6 32.8 68.8 34.4 ms ms r adin adin input resistance v dd = 48v, adin = 3v l 3 10 m clkin, clkout, gpiov clkin(th) clkin input threshold l 0.7 1 1.3 v f clkin(max) maximum clkin frequency l 25 mhz i clkin(in) clkin input current v clkin = 5v l 5 10 a i clkout clkout output current v clkin = 0v, v clkout = 0v l C70 C100 C130 a v gpio(th) gpio input threshold v gpio rising l 1.06 1.22 1.32 v v gpio(hyst) gpio input hysteresis 36 mv v gpio(ol) gpio output low voltage i gpio = 8ma l 0.15 0.4 v i gpio(in) gpio input leakage current v gpio = 5v l 0 1 a i 2 c interface (v dd = 48v) v adr(h) adr0, adr1 input high threshold l 1.9 2.4 2.7 v v adr(l) adr0, adr1 input low threshold l 0.3 0.6 0.9 v i adr(in) adr0, adr1 input current adr0, adr1 = 0v, 3v l 13 a i adr(in,z) allowable leakage when open l 7 a v od(ol) sdao, sdao , output low voltage i sdao , i sdao = 8ma l 0.15 0.4 v i sda,scl(in) sdai, sdao, sdao , scl input current sdai, sdao, sdao , scl = 5v l 0 1 a downloaded from: http:///
ltc 2946 5 2946fa for more information www.linear.com/ltc2946 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive. all voltages are referenced to ground, unless otherwise noted. note 3: an internal shunt regulator limits the intv cc pin to a minimum of 5.8v. driving this pin to voltages beyond 5.8v may damage the part. this pin can be safely tied to higher voltages through a resistor that limits the current below 35ma. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd is from 4v to 100v, unless otherwise noted. (note 2) note 4: internal clamps limit the scl and sdai pins to a minimum of 5.9v. driving these pins to voltages beyond the clamp may damage the part. the pins can be safely tied to higher voltages through resistors that limit the current below 5ma. note 5: sense is defined as v sense + C v sense C note 6: tue = (actual code C ideal code)/4096 ? 100% where ideal code is derived from a straight line passing through code 0 at 0v and theoretical code of 4096 at v fs . note 7: guaranteed by design and not subject to test. symbol parameter conditions min typ max units v sda,scl(th) sdai, scl input threshold l 1.5 1.8 2.1 v v sda,scl(cl) sdai, scl clamp voltage i sdai , i scl = 3ma l 5.9 6.4 6.9 v i 2 c interface timing f scl(max) maximum scl clock frequency l 400 khz t low scl low period l 0.65 1.3 s t high scl high period l 50 600 ns t buf(min) bus free time between stop/start condition l 0.12 1.3 s t hd,sta(min) hold time after (repeated) start condition l 140 600 ns t su,sta(min) repeated start condition setup time l 30 600 ns t su,sto(min) stop condition setup time l 30 600 ns t hd,dati(min) data hold time input l C100 0 ns t hd,dato(min) data hold time output l 300 600 900 ns t su,dat(min) data setup time l 30 100 ns t sp(max) maximum suppressed spike pulse width l 50 110 250 ns t rst stuck bus reset time scl or sdai held low l 25 33 ms c x scl, sdai input capacitance (note 7) 5 10 pf typical performance characteristics v dd supply current intv cc supply current intv cc load regulation v dd supply voltage (v) 0 20 supply current (a) 26 20 40 80 60 1000 22 800700 24 900 100 2946 g01 shutdown normal intv cc supply voltage (v) 2 15 supply current (a) 30 3 4 5 900 20 700600 25 800 6 2946 g02 shutdown normal load current (ma) 0 4.8 intv cc voltage (v) 5.0 2 4 8 6 5.2 4.9 5.1 10 2946 g03 downloaded from: http:///
ltc 2946 6 2946fa for more information www.linear.com/ltc2946 typical performance characteristics intv cc shunt regulator load regulation sense input current adr voltage with current source or sink scl/sdai loaded clamp voltage vs load current gpio, sdao, sdao loaded output low voltage vs load current adc integral nonlinearity (adin) adc total unadjusted error (adin) intv cc line regulation adc differential nonlinearity (adin) v dd supply voltage (v) 0 3.5 intv cc output voltage (v) 4.5 20 40 80 60 5.5 4.0 5.0 100 2946 g04 intv cc shunt current (ma) 0 6.20 intv cc voltage (v) 6.30 10 20 30 6.40 6.25 6.35 40 2946 g05 sense voltage (v) 0 C20 sense current (a) 0 20 40 60 80 100 20 40 60 80 100 sense + 2946 g06 sense C i adr (a) C10 2.0 2.51.5 1.0 0 C5 5 10 0.5 0 3.0 v adr (v) 2946 g07 i load (ma) 0.01 6.4 v sda,scl(cl) (v) 6.5 0.10 1.00 10.00 6.3 6.26.1 6.0 6.6 2946 g08 i od (ma) 0 0 v od(ol) (v) 0.2 2 4 8 6 0.4 0.1 0.3 10 2946 g09 code 0 C0.10 adc tue (%) C0.05 0 0.05 0.10 1024 2048 3072 4096 2946 g10 code 0 0.1 0.2 0 C0.1 2048 1024 3072 4096 C0.2 C0.3 0.3 adc inl (lsb) 2946 g11 code 0 0.1 0.2 0 C0.1 2048 1024 3072 4096 C0.2 C0.3 0.3 adc dnl (lsb) 2946 g12 downloaded from: http:///
ltc 2946 7 2946fa for more information www.linear.com/ltc2946 adc total unadjusted error (?sense) typical performance characteristics internal clock frequency over temperature v dd supply current over clkin frequency current sense amplifier offset drift over temperature adc conversion time over internal clock frequency current sense amplifier offset drift over input common mode adc integral nonlinearity (?sense) adc differential nonlinearity (?sense) code 0 C0.2 adc tue (%) C0.1 0 0.1 0.2 1024 2048 3072 4096 2946 g13 code 0 0.1 0.2 0 C0.1 2048 1024 3072 4096 C0.2 C0.3 0.3 adc inl (lsb) 2946 g14 code 0 0.1 0.2 0 C0.1 2048 1024 3072 4096 C0.2 C0.3 0.3 adc dnl (lsb) 2946 g15 temperature (c) C50 internal clock frequency (khz) 254.4254.3 254.2 0 50 C25 25 75 100 125 254.1254.0 254.5 2946 g16 temperature (c) C50 offset drift (lsb) 64 2 0 50 C25 25 75 100 125 0 C2 8 2946 g17 calibration off calibration on common mode voltage (v) 0 offset drift (lsb) 64 2 50 25 75 100 0 C2 8 2946 g18 initial calibration done at v cm = 48v no calibration thereafter calibration off calibration on f clkin (mhz) 0 850 supply current (a) 950 5 10 20 15 1050 900 1000 25 2946 g19 internal clock frequency (khz) 100 20 conversion time (ms) 60 150 200 250 350 300 100 40 80 400 2946 g20 snapshot measurement of adin downloaded from: http:///
ltc 2946 8 2946fa for more information www.linear.com/ltc2946 pin functions adin: adc input. the onboard adc measures voltages between 0 v and 2.048 v with respect to gnd or intv cc . tie to ground if unused. see table 3 in the applications information section for details. adr1, adr0: i 2 c device address inputs. connecting these pins to intv cc , gnd, or leaving the pins open configures one of nine possible addresses. see table 1 in the ap- plications information section for details.clkin : clock input. connect to ground to use the internal 5% clock. for improved accuracy, connect to an external crystal oscillator circuit or drive with an external clock. clkout: clock output. connect to an external crystal oscillator circuit. leave open if unused. exposed pad : exposed pad may be left open or con - nected to device ground. for best thermal performance, connect to a large pcb area.gnd: device ground. gpio1: general purpose input/output ( open drain). con - figurable to general purpose output or input. ti e to ground if unused. see table 9 in the applications information section for details.gpio2: general purpose input/output ( open drain). con - figurable to general purpose output, input or accumulation enable ( acc) to gate internal accumulators. tie to ground if unused. see table 9 in the applications information section for details. gpio3: general purpose input / output ( open drain ). configurable to general purpose output, input or alert . as alert , it is pulled to ground when a fault occurs to alert the host controller. a fault alert is enabled by setting the corresponding bit in the alert registers, as shown in tables 5 and 8. tie to ground if unused. see table 9 in the applications information section for details. intv cc : internal low voltage supply input / output. this pin is used to power internal circuitry. it can be configured as a direct input for a low voltage supply, as a linear regula - tor from a higher voltage supply connected to v dd , or as a shunt regulator. connect this pin directly to a 2.7 v to 5.8v supply if available. when intv cc is powered from an external supply, short the v dd pin to intv cc . if v dd is connected to a 4 v to 100 v supply, intv cc becomes the 5v output of an internal series regulator that can supply up to 10 ma to external circuitry. for even higher supply voltages, or if a floating topology is desired, intv cc can be used as a 6.3 v shunt regulator. connect the supply to int v cc through a resistor or current source that limits the shunt regulator current to less than 35 ma. an undervolt- age lockout circuit disables the adc when the voltage at this pin drops below 2.5 v. connect a bypass capacitor of 0.1f or greater from this pin to ground. if an external load is present, for loop stability use a bypass capacitor of 0.22f or greater.scl: i 2 c bus clock input. data at the sdai pin is shifted in or out on rising edges of scl. this pin is driven by an open - collector output from a master controller. an external pull-up resistor or current source is required and can be placed between scl and v dd or intv cc . the voltage at scl is internally clamped to 6.4v typically. downloaded from: http:///
ltc 2946 9 2946fa for more information www.linear.com/ltc2946 sdai: i 2 c bus data input. used for shifting in address, command or data bits. this pin is driven by an open- collector output from a master controller. an external pull-up resistor or current source is required and can be placed between sdai and v dd or intv cc . the voltage at sdai is internally clamped to 6.4 v typically. tie to sdao for normal i 2 c operation. sdao: ltc2946 only. i 2 c bus data output. open-drain output used for sending data back to the master control- ler or acknowledging a write operation. an external pull-up resistor or current source is required. tie to sdai for normal i 2 c operation. sdao : ltc2946-1 only. inverted i 2 c bus data output. open-drain output used for sending data back to the master controller or acknowledging a write operation. data is inverted for convenience of opto-isolation. an external pull-up resistor or current source is required. the ltc2946-1 cannot be used in nonisolated i 2 c applications without additional components. sense + : supply voltage and current sense input. used as a supply and current sense input for internal current sense amplifier. the voltage at this pin is monitored by the onboard adc with a full-scale input range of 102.4 v. see figure 20 for recommended kelvin connection.sense ? : current sense input. connect an external sense resistor between sense + and sense C . the differential voltage between sense + and sense C is monitored by the onboard adc with a full-scale sense voltage of 102.4 mv. v dd : high voltage supply input. this pin powers an in - ternal series regulator with input voltages ranging from 4v to 100 v and produces 5 v at intv cc when v dd is above 8v . connect a bypass capacitor of 0.1 f or greater from this pin to ground if an external load is present on the intv cc pin. the onboard 12- bit adc can be configured to monitor the voltage at v dd with a full - scale input range of 102.4 v. pin functions downloaded from: http:///
ltc 2946 10 2946fa for more information www.linear.com/ltc2946 block diagram timing diagram t sp t buf t su,sto t sp t hd,sta start condition stop condition t su,sta t hd,dati t hd,dato repeated start condition repeated start condition t su,dat sda scl t hd,sta 2946 td 12 C + C + C + C + 2946bd sdao/ sdao ltc2946/ ltc2946-1 sdai clkout sense C sense + v dd v ref 2.048v intv cc adin clkin gnd adr0 voltage current power time counter charge energy i 2 c decoder adr1 gpio3 1.22v gpio2 scl 20x 6.3v 735k 15k 735k 15k 6.4v 6.4v 1.22v gpio1 1.22v osc 5v ldo ? adc 15 16 1 2 13 11 9 10 3 4 5 14 12 8 7 6 downloaded from: http:///
ltc 2946 11 2946fa for more information www.linear.com/ltc2946 c2 0.1f c333pf v in 4v to 100v r sns 0.02 v out v adin gp output x1: abls-4.000mhz-b2-t r1 2k r2 2k r3 2k 3.3v v dd sclsda int gnd adr0 scl v dd intv cc sdai sdao gpio1 alert adr1 sense + accumulate sense C ltc2946 x1 p gpio3 clkout gndgpio2 r42k 3.3v clkin 2946 f01 adin c433pf operation the ltc2946 accurately monitors current, voltage and power of any supply rail from 0 v to 100 v. an internal linear regulator allows the ltc2946 to operate directly from a 4 v to 100 v rail, or from an external supply voltage between 2.7v and 5.8 v. quiescent current is less than 1.3 ma in normal operation. enabling shutdown mode via the i 2 c interface reduces the quiescent current to below 40a. the onboard 12- bit analog-to-digital converter ( adc) runs either continuously or on demand using snapshot mode. there are seven continuous scan modes that can be selected via i 2 c. these modes configure the adc to re- peatedly measure the differential voltage between sense + and sense C ( full-scale 102.4 mv), the voltage at sense + or v dd pin ( full-scale 102.4 v) and the voltage applied to adin pin ( full-scale 2.048 v) at internally set duty cycles. see the applications information section for more details. the conversion results are stored in onboard registers. in snapshot mode, the ltc2946 performs a single mea - surement of one selected voltage or current. a status bit in the status2 register monitors the adcs conversion progress; when complete, the conversion result is stored in the corresponding data registers. the gpio1 to gpio3 pins are general purpose inputs or general purpose open-drain outputs. gpio2 may also be configured as an enabling input for the accumulators. similarly, gpio3 may be configured as an alert output. onboard logic stores the minimum and maximum values for each adc measurement, calculates power data by digitally multiplying the stored current and voltage data, and optionally triggers an alert by pulling the gpio3 pin low when the adc measured value falls outside the programmed window thresholds. the ltc2946 includes accumulators that integrate the measured current and power over time to produce charge and energy values. the accumulators integrate at a rate determined either with an internal trimmed 5% clock, a precision clock generated from an external crystal, or an external clock. the accumulators can be preset with a value and optionally generate an alert when they overflow. the ltc2946 includes an i 2 c interface to access the onboard data registers and to program the alert thresh- old, configuration and control registers. tw o three-state pins, adr1 and adr0, are decoded to allow nine device addresses ( see table 1). the sda pin is split into sdai (input) and sdao ( output, ltc2946) or sdao ( output , ltc2946-1) to facilitate opto - isolation. tie sdai and sdao together for normal, nonisolated i 2 c operation. figure 1. high side power, energy and charge monitor using the ltc2946 applications information the ltc2946 offers a compact and complete solution for high and low side power monitoring with integrated energy and charge accumulators. with an input common mode range of 0 v to 100 v and a wide input supply operating voltage range from 2.7 v to 100 v, this device is ideal for a wide variety of power management applications including automotive, industrial and telecom infrastructure. the basic application circuit shown in figure 1 provides monitoring of high side current with a 0.02 resistor (5.12 a full-scale), input voltage (102.4 v full-scale) and an external voltage (2.048v full-scale), all using an internal 12-bit adc. downloaded from: http:///
ltc 2946 12 2946fa for more information www.linear.com/ltc2946 applications information is shown where the adc periodically calibrates the cur- rent sense amplifier with other voltages sequenced for conversions in between. tw o factors need to be considered when selecting between these configurations: 1. presence of load current harmonics in sync with the windows when the adc is not sampling the current. the user can improve measurement accuracy of the load current signal with such harmonics by selecting a higher duty cycle for sense. for most complete coverage, the adc can be configured to continuously measure the current by setting ca[2:0] to 110. 2. increasing the duty cycle for current measurement will result in less frequent updates of the current sense amplifiers offset and the supply voltage values, hence the amount they drift with respect to time and temperature determines the best configuration to use. an on-demand update can also be done with a single i 2 c write transaction to the ctrla register, which will command new measurements of the current sense amplifiers offset and the supply voltage. the results will be used for offset calibration and for providing the voltage value for the multiplier. for example, if ca[6:5] is set to code 11, and ca[2:0] is set to 110, a new offset and voltage values will be produced two adc conversions after the i 2 c write transaction. the adc will continuously measure the current thereafter. the timing diagram shown in figure 2 d illustrates the sequence in which the power and accumulator data are generated following conversions in the default configura - tion. at t 1 , the adc has just finished a conversion of the current ( sense) signal. the time counter is incremented by one count while the new current data at t 1 is added to the charge accumulator. a new power value is generated by multiplying i (t1) with the previous voltage ( v in ) data that is then added to the energy accumulator. from t 1 to t 3 , the systematic offset of the current sense amplifier is measured and stored. the adc then performs a conversion on v in . a calibration is done again at t 4 before the adc converts sense. the charge and energy accumulators are incremented at t 2 , t 3 , t 4 , t 5 , t 6 and t 7 , with current and power data from time t 1 . the timer counter will keep track data converter, multiplier and accumulator the ltc2946 features an onboard , 12- bit ? adc that inherently averages input signal and noise over the con- version time window. the differential voltage between sense + and sense C ( sense) is monitored with 25 v/ lsb resolution (102.4 mv full-scale) to allow accurate measurement of the load current across very low value shunt resistors. the supply voltage at v dd or sense + is directly measured with 25 mv/lsb resolution (102.4 v full-scale). the voltage at the uncommitted adin pin can also be measured with 0.5 mv/lsb resolution (2.048 v full- scale) to allow monitoring of an arbitrary external voltage. the supply voltage data is derived from v dd , sense + or adin depending on the external application circuit. sense + is selected by default as it is normally connected to the supply voltage as shown in figure 4 (4 a to 4 c) and figure 5b. in negative supply voltage systems, such as shown in figure 5 d, v dd is used to measure the supply voltage at gnd with respect to the device ground. for positive and negative supply voltages of more than 100 v, as shown in figure 5 a and figure 5 c, external resistors can be used to divide down the voltage for adin to measure the supply voltage. ca[4:3] in the ctrla register select between v dd , sense + and adin for supply voltage data. more details can be found in table 3. a 24- bit power value is generated by digitally multiplying the 12- bit load current data with the 12- bit supply voltage data . 1 lsb of power is 1 lsb of voltage multiplied by 1 lsb of sense ( current). the result is held in the three adjacent power registers (table 2). during conversions, the data converters input is mul - tiplexed to measure four voltages : sense, the current sense amplifiers offset, v dd or v sense + , and v adin at various duty cycle by configuring ca[6:5] and ca[2:0] in the ctrla register ( table 3). some configurations are shown in figure 2 (2 a to 2 c) to illustrate the various conversion timing sequences. in figure 2 a, it is shown that upon power-up or after an i 2 c write transaction to the ctrla register the adc will first measure the current sense amplifiers offset ( calibration) and again after every other conversion which can be either v adin , the supply voltage ( v dd or v sense + ) or the load current ( sense). figure 2 b shows periodic calibration performed every 16 conversions. in figure 2 c a more specific configuration downloaded from: http:///
ltc 2946 13 2946fa for more information www.linear.com/ltc2946 meas adin n = 1 meas adin n = 1 cal cal cal meas v n = 2 meas i n = 3 power-up orctrla written meas i n = 128 meas i n = 129 meas i n = 256 2946 f02 meas n = 1 cal cal meas n = 2 meas n = 3 power-up orctrla written meas n = 16 meas n = 1 meas n = 2 meas cal cal meas meas v meas i cal cal cal meas i power-up orctrla written 16.4ms t 8 new power = p(t 8 ) new current= i(t 8 ) 16.4ms t 7 power = p(t 1 ) current= i(t 1 ) 16.4ms t 6 power = p(t 1 ) current= i(t 1 ) 16.4ms t 5 power = p(t 1 ) current= i(t 1 ) 16.4ms t 4 power = p(t 1 ) current= i(t 1 ) 16.4ms t 3 power = p(t 1 ) current= i(t 1 ) 16.4ms t 2 t 1 power = p(t 1 ) current= i(t 1 ) new power = p(t 1 ) new current= i(t 1 ) (2b) current sense amplifier calibrated every 16 conversions, ca[6:5] = 01 (2c) the adc conversion sequence for ca[6:5] = 10 and ca[2:0] = 101 (2d) default adc conversion sequence figure 2 (2a) current sense amplifier calibrated every conversion, ca[6:5] = 00 applications information of the number of accumulations that have occurred. at t 8 , new current and power data becomes available and these values are added to the charge and energy accumulators . for other ca configurations, the charge and energy ac - cumulators behave similarly; during calibration and when not measuring current the last current value will be used for accumulation and calculation of power. a 12- bit digital word corresponding to each measured voltage is stored in two adjacent registers out of the six total adc data registers ( sense msb/lsb, v in msb/ lsb, and adin msb/lsb), with the eight msbs in the first register and the four lsbs in the second ( see table?2). the lowest 4 bits in the lsb registers are set to 0. these data registers are updated immediately following the cor - responding adc conversion. the 4- byte time counter keeps track of the elapsed time during which current and power measurements have been added to the charge and energy accumulators, respectively . at 16.395 ms per count it will keep counts up to 2.23 years (see table 15). dividing the energy/charge by the time in the timer will yield the average power/current over the time interval in the timer. the charge accumulator is a 36-bit register with the most significant 32- bits accessible , hence one charge bit is equivalent to one timer tick of 16 (2 4 ) counts of current. similarly, the energy accumulator is a 48- bit register with the most significant 32- bits ac- cessible, hence one energy bit is equivalent to one timer tick of 65536 (2 16 ) counts of power. with current and power at full-scale the charge and energy accumulators are capable of storing 3.2 days of data which translates to several months at nominal current and power levels. downloaded from: http:///
ltc 2946 14 2946fa for more information www.linear.com/ltc2946 since the accumulators contain multiple bytes of data, a single page read transaction of the accumulators is required to ensure the data is coherent. all the accumula - tors are writable, allowing them to be preloaded with given values. the ltc2946 can then be configured to generate an overflow alert after a specified amount of energy or charge has been delivered or when a preset amount of time has elapsed. a snapshot mode is also included which makes a measure - ment of a single selected voltage ( either sense, v dd or v sense + , or v adin ). to make a snapshot measurement, write the 2- bit code of the desired adc channel to ca[4:3] and code 111 to ca[2:0] using a write byte command to the ctrla register. when the write byte command is completed, the adc converts the selected voltage and the busy bit s2[3] in the status2 register ( see table 10) will be set to indicate that the conversion is in progress. after completing the conversion, the adc will halt and the busy bit will reset to indicate that the data is ready. an alert may be generated at the end of a snapshot conver - sion by setting bit al2[7] in the alert2 register ( table 8). to make another snapshot measurement, rewrite the ctrla register. in snapshot mode, the power registers, time counters, charge and energy accumulators are not refreshed. crystal oscillator/external clockaccurately measuring energy / charge by integrating power / current requires a precise integration period. the on-chip clock of the ltc2946 is trimmed to within 5%. to enable timekeeping with the on-chip clock, tie clkin to gnd and leave clkout open. for better accuracy, a crystal oscillator or resonator may be connected to the clkin and clkout pins, as shown in figure 1. alternately, an external clock between 1 mhz and 25 mhz may be applied to clkin with clkout left unconnected. the clock frequency at clkin is divided by 4 the value in the clk_div register ( see table 13) to generate an internal clock with targeted frequency of 250 khz for the data converters delta-sigma modulator. with an external clock or crystal, the sampling frequency of the adc can be adjusted by configuring the clk_div register ( register 43 h ). limit the sampling clock to between 100khz and 400 khz and at least 20 khz above or below f in . the delta-sigma adc provides inherent averaging of the input signal such that an anti-aliasing filter is not required in most applications. however, noise ripple ( f in ) occurring at integer multiples of the modulator sampling frequency (f s ) can still pose problems. figure 3 shows how the sampling frequency as a function of the input frequency affects the amount of error. when f s = f in , in the worst case the input signal may be sampled entirely at its peak applications information figure 3. waveforms showing the effect of aliasing 0s 10s 20s 30s 40s 50s 60s 70s 80s 100s 90s 2946 f03 f s = 0.9 ? f in t in f s = 1.1 ? f in f s = f in t s t in t s t in t s downloaded from: http:///
ltc 2946 15 2946fa for more information www.linear.com/ltc2946 (or trough) resulting in an average output value of v peak (or v trough ). the actual average value of the input is ? ? ( v peak C v trough ). slightly adjusting the sampling frequency will remove the error as samples representative of the entire waveform are averaged over the conversion period. this is illustrated in the waveforms corresponding to f s = 0.9 f in and f s = 1.1 f in . the input can be seen to get sampled at multiple instances between the peak and trough. averaging sufficient number of samples will then yield the correct result.flexible power supply to ltc2946 the ltc2946 can be externally configured to derive power from a wide range of supplies. the ltc2946 includes an onboard linear regulator to power the low voltage inter - nal cir cuitry connected to the intv cc pin from high v dd voltages. the linear regulator operates with v dd voltages from 4 v to 100 v, and a shunt regulator is available for voltages above 100 v. the linear regulator produces a 5 v output capable of supplying 10 ma at the intv cc pin when v dd is greater than 8 v. the regulator is disabled when the junction temperature rises above 150 c, and the output is protected against accidental shorts. bypass capacitors of 0.1 f, or greater, at both the v dd and intv cc pins are recommended for optimal transient performance. note that operation with high v dd voltages can result in significant power dissipation, and care is required to ensure that the maximum operating junction temperature stays below 125c. for improved thermal resistance, use the dfn package and solder the exposed pad to a large copper region on the pcb.figure 4 a shows the ltc2946 being used to monitor an input supply that ranges from 4 v to 100 v. no secondary supply is needed since v dd can be connected directly to the input supply. if the ltc2946 is used to monitor an input supply of 0 v to 100 v, it can derive power from a wide range secondary supply connected to the v dd pin as shown in figure 4 b. the sense + / C pins can be biased independently of the parts supply voltage. alternatively, if a low voltage supply is present it can be connected to the intv cc pin, as shown in figure 4 c, to minimize on- chip power dissipation. when intv cc is powered from a secondary supply, connect v dd to intv cc . for supply voltages above 100 v, the shunt regulator at int v cc can be used in both high and low side configura- tions to provide power to the ltc2946 through an external shunt resistor, r shunt . figure 5 a shows a high side power applications information figure 4 (4c) ltc2946 derives power from a low voltage secondary supply (4a) ltc2946 derives power from the supply being monitored (4b) ltc2946 derives power from a wide range secondary supply sense + sense C v dd intv cc ltc2946 gnd v out c2 r sns v in 4v to 100v 2946 f04a sense + sense C v dd intv cc ltc2946 gnd v out c2 r sns v in 0v to 100v 4v to 100v 2946 f04b sense + sense C v dd intv cc ltc2946 gnd v out r sns v in 0v to 100v 2.7v to 5.9v 2946 f04c downloaded from: http:///
ltc 2946 16 2946fa for more information www.linear.com/ltc2946 figure 5 monitor with an input monitoring range beyond 100 v in a high side shunt regulator configuration. the device ground is separated from ground through r shunt and clamped at 6.3v below the input supply. note that due to the different ground levels, the i 2 c signals from the part need to be level shifted for communication with other ground referenced components. the bus voltage is measured with a resistor string connected to adin. set ca[7] in the ctrla register so that the adc measures adin with reference to intv cc instead of gnd. the measurement range at adin is then from intv cc to intv cc C 2.048v. figure 5 b shows a high side rail-to-rail power monitor which derives power from a secondary supply greater than 100 v. the voltage at intv cc is clamped at 6.3 v above ground in a low side shunt regulator configuration to power the part. in low side power monitors, the device ground and the current sense inputs are connected to the negative terminal of the input supply as shown in figure 5c. the low side shunt regulator configuration allows operation with input supplies above 100 v by clamping the voltage at intv cc . r shunt should be sized according to the following equation: v s(max) ? v ccz(min) i cc(absmax) r shunt v s(min) ? v ccz(max) i cc(max) + i load(max) v s(max) ? 5.8v 35ma r shunt v s(min) ? 6.7v 1ma + i load(max) (1) where v s(max) and v s(min) are the operating maximum and minimum limits of the supply. i load(max) is the maxi- mum external current load that is connected to the shunt regulator. the shunt resistor must also be rated to safely applications information (5c) ltc2946 derives power through a low side shunt regulator in a low side current sense topology (5d) ltc2946 derives power from the supply monitored in a low side current sense topology (5a) ltc2946 derives power through a high side shunt regulator (5b) ltc2946 derives power through a low side shunt regulator in a high side current sense topology sense + sense C adin intv cc ltc2946 gnd v out c2 r sns r2 v in >100v 2946 f05a v dd r shunt r1 sense + sense C v dd intv cc ltc2946 gnd v out c2 r sns r shunt v in 0v to 100v >100v 2946 f05b sense C sense + adin intv cc ltc2946 v out c2 r sns r2 > C100v 2946 f05c gnd gnd v dd r shunt r1 sense + sense C intv cc ltc2946 v out c2 r sns v neg (C4v to C100v) 2946 f05d gnd gnd v dd downloaded from: http:///
ltc 2946 17 2946fa for more information www.linear.com/ltc2946 dissipate the worst-case power. as an example, consider the C48 v telecom system where the supply operates from C36v to C72 v and the shunt regulator is used to supply an external load up to 4 ma. r shunt needs to be between 1.9k and 5.9 k according to the previous equation, and for reduced power dissipation, a larger resistance is advan - tageous. the worst-case power dissipated in an r shunt of 5.36 k is calculated to be 0.8 w. three 0.5 w rated 1.8 k resistors in series would suffice for this example. if the supply input is below 100 v, the shunt resistor is not required and v dd can be connected to gnd of the supply as shown in figure 5d. supply undervoltage lockout during power-up, the internal i 2 c logic and the adc are enabled when either v dd or intv cc rises above its under- voltage lockout threshold. during power-down, the adc is disabled when v dd and intv cc fall below their respective undervoltage lockout thresholds. the internal i 2 c logic is reset when v dd and intv cc fall below their respective i 2 c reset thresholds. shutdown mode the ltc2946 includes a low quiescent current shutdown mode, controlled by bit cb[6] in the ctrlb register (t able 4). setting cb[6] puts the part in shutdown mode, powering down the adc, internal reference and onboard linear regulator. the internal i 2 c bus remains active, and although the adr1 and adr0 pins are disabled, the device will retain the most recently programmed i 2 c bus address. all onboard registers retain their contents and can be accessed through the i 2 c interface. to re-enable adc conversions, reset bit cb[6] in the ctrlb register. the analog circuitry will power up and all registers will retain their contents.the onboard linear regulator is disabled in shutdown mode to conserve power. if the onboard linear regulator is used to power external i 2 c bus related circuitry such as opto- couplers or pull-ups, i 2 c communication will be lost when the part is shut down. the ltc2946 would then have to be reset by cycling its power to come out of shutdown. if low i q mode is not required, ensure bit cb[6] in the ctrlb register is masked off during software development. it is recommended that external regulators be used in such applications if powering down the ltc2946 is desirable. as an added layer of protection against this scenario, bit cb[4] in the ctrlb register can be set during system configuration to enable the ltc2946 to automatically exit shutdown mode when the i 2 c lines are low for more than 33ms ( which can be a result of accidental shutdown of the ltc2946s linear regulator powering the i 2 c). the user can elect to be alerted of this event by setting bit al2[3] in the alert2 register ( table 8). quiescent current drops below 40 a in shutdown mode with the internal regulator disabled.configuring the gpio pins the ltc2946 has three gpio pins configurable through the gpio_cfg register ( table 9) to be used as general purpose input/output pins. as general purpose inputs, gpio1 through gpio3 can be either active high or low. in addition, gpio2 can also be used as an accumulation enable input by writing bits cb [3:2] = [10] to allow integra - tion of the time counter, charge and energy accumulators. gpio1 through gpio3 have comparators monitoring the voltage on these pins with a threshold of 1.22 v, the results of which may be read from bits s2[6:4] in the status2 register, as shown in table 10. an alert may be generated when gpio1 or gpio2 are active as inputs by setting bits al2[6] and al2[5], respectively, in the alert2 register. gpio1-3 can be pulled low as general purpose outputs, which are otherwise high impedance. gpio3 is by default an alert output that pulls low when an alert event is present. to pull gpio 3 ( alert ) low in the absence of an alert event, set gc[7] of the gpio3_ctrl register ( table 12). clearing this bit will release the gpio 3 ( alert ). gc[7] does not have an effect on gpio3 if it is not configured as an alert output. likewise, gc[6] does not affect gpio3 if it is not configured as a general purpose output. gc[7] is set whenever an alert event occurs irrespective of gpio3's configuration. reset gc[7] before reconfiguring gpio3 to alert . applications information downloaded from: http:///
ltc 2946 18 2946fa for more information www.linear.com/ltc2946 i 2 c reset the accumulators can be programmed to reset themselves after the host reads the last byte (3 fh) of the accumulator data by writing bits cb[1:0] to [01] in the ctrlb register (table 4). this feature removes the need to issue a reset command after polling the ltc2946 for accumulated data. the accumulators will continue to accumulate after the reset. to reset the accumulators without such read com - mand, write bits cb[1:0] to [10]. the accumulators will stay reset if cb [1:0] = [10]. all registers are reset when cb [1:0] = [11], and these bits will then auto-reset to [00]. the adc sequencing configuration is preserved through the i 2 c reset, regardless of the ctrla register having reset. to change the sequencing configuration after such resets, rewrite the ctrla register. storing minimum and maximum values the ltc2946 compares each measurement including the calculated power with the stored values in the respective min and max registers for each parameter ( table 2). if the new conversion is beyond the stored minimum or maximum values, the min or max registers are updated with the new values. the min and max of the registers are refreshed at the end of their respective adc conver - sions i n continuous scan modes and snapshot mode. they are also refreshed if the adc registers are written via the i 2 c bus with values beyond the stored values. to initiate a new peak hold cycle, write all 1 s to the min registers and all 0 s to the max registers via the i 2 c bus. these registers will be updated when the next respective adc conversion is done. the ltc2946 also includes min and max threshold reg - isters ( table 2) for the measured parameters including the calculated power. at power-up, the maximum thresholds are set to all 1 s, and minimum thresholds are set to all 0s, effectively disabling them. the thresholds can be reprogrammed to any desired value via the i 2 c bus. fault alert and resetting faults as soon as a measured quantity falls below the minimum threshold or exceeds the maximum threshold, the ltc2946 sets the corresponding flag in the status 1 ( table 6) reg - ister and latches it into the fa u lt1 ( table 7) register ( see figure 6). other events such as gpio state change, stuck bus wake-up and accumulator overflow have their present status in the status 2 ( table 10) register and any fault is latched in the fau lt2 ( table 11) register. the gpio3 pin is pulled low if the appropriate bit in the alert 1 ( table 5) and alert 2 ( table 8) registers is set and it is configured as alert output. more details on the alert behavior can be found in the alert response protocol section. an active fault indication can be reset by writing zeros to the corresponding fault register bits or setting bit cb[5] in the ctrlb register. if bit cb[5] is set, reading the fau lt1 or fau lt2 register will cause the corresponding register to reset. all fault register bits are also cleared if the v dd and intv cc fall below their respective i 2 c logic reset threshold. note that faults that are still present, as indicated in the status1 and status2 registers, will immediately reappear. when accumulators ( time, charge and energy) overflow, the corresponding bits in the status2 register are set and will stay set. the accumulator overflow bits in the fau lt2 register will reappear after they have been cleared via i 2 c since the status2 register continues to indicate overflow faults. applications information figure 6. ltc2946 fault alert generation blocks digital comparator logic latch status reset fault alert ena_alert_response measured data threshold data 2946 f06 downloaded from: http:///
ltc 2946 19 2946fa for more information www.linear.com/ltc2946 applications information figure 7. general data transfer over i 2 c sda scl s p a6 - a0 b7 - b0 b7 - b0 1 - 7 1 - 7 1 - 7 8 8 8 9 9 9 start condition stop condition address ack data data ack ack r/ w 2946 f06 figure 8. ltc2946 serial bus sda write byte protocol figure 9. ltc2946 serial bus sda write word protocol figure 10. ltc2946 serial bus sda write page protocol figure 11. ltc2946 serial bus sda read byte protocol figure 12. ltc2946 serial bus sda read word protocol figure 13. ltc2946 serial bus sda read page protocol protocol s address 1 1 0 a3:a0 from master to slave from slave to master a: acknowledge (low)a : not acknowledge (high) r: read bit (high) command d ata x x b5:b0 0 w 0 0 0 b7:b0 a a a p 2946 f08 w : write bit (low) s: start condition p: stop condition s address 1 1 0 a3:a0 command d ata d ata x x b5:b0 0 w 0 0 0 0 2946 f09 b7:b0 b7:b0 a a a a p s address 1 1 0 a3:a0 command 0 x x b5:b0 0 w 0 0 2946 f10 a a a p b7:b0 d ata 0 a b7:b0 d ata 0 a ... ... b7:b0 d ata s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata x x b5:b0 0 w 0 0 2946 f11 a a a p s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata x x b5:b0 0 w 0 0 2946 f12 a 0 a b7:b0 d ata a a p s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata x x b5:b0 0 w 0 0 2946 f13 a 0 a b7:b0 d ata a a p ... ... b7:b0 d ata if it is necessary to clear accumulator overflow fault(s), the recommended procedure is: 1. read the accumulators 2. store these values in an external memory 3. issue a reset to the accumulators by writing bits cb[1:0] to [10]. then disable reset by writing bits cb[1:0] to [00]. 4. write the stored values back to the accumulators steps 2 and 4 can be skipped if there is no need to continue the accumulation from present values. i 2 c interface the ltc2946 includes an i 2 c/smbus-compatible inter- face to provide access to the onboard registers. figure 6 shows a general data transfer format using the i 2 c bus. the ltc2946 is a read/write slave device and supports the smbus read byte, write byte, read word and write word protocols. the ltc2946 also supports extended read and write commands that allow reading or writing more than two bytes of data. when using the read/write word or extended read and write commands, the bus master issues an initial register address and the internal register ad dress downloaded from: http:///
ltc 2946 20 2946fa for more information www.linear.com/ltc2946 pointer automatically increments by 1 after each byte of data is read or written. after the register address reaches 43h, it will roll over to 00 h and continue incrementing. a stop condition resets the register address pointer to 00 h. the data formats for the above commands are shown in figure 7 through figure 13. note that only the read byte command is available to the e 7 and e 8 ( mfr _ special _ id ) registers (table 2). i 2 c device addressing nine distinct i 2 c bus addresses are configurable using the three-state pins adr0 and adr1, as shown in table 1. adr0 and adr1 should be tied to intv cc , to gnd, or left floating ( nc) to configure the lower four address bits. during low power shutdown, the address select state is latched into memory powered from standby supply. address bits a6, a5 and a4 are permanently set to 110 b and the least significant bit is the r/ w bit. in addition, all ltc2946 devices will respond to a common mass write address 1100_110 b; this allows the bus master to write to several ltc2946s simultaneously, regardless of their individual address settings. the ltc2946 will also respond to the standard ara address 0001_ 100b if the gpio3 ( aler t) pin is asserted. see the alert response protocol section for more details. the ltc2946 will not respond to the ara address if no alerts are pending. start and stop conditions when the i 2 c bus is idle, both scl and sda are in the high state. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl stays high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl stays high. the bus is then free for another transmission.stuck-bus reset the ltc2946 i 2 c interface features a stuck-bus reset timer to prevent it from holding the bus lines low indefinitely if the scl signal is interrupted during a transfer. the timer starts when either scl or sdai is low, and resets when both scl and sdai are pulled high. if either scl or sdai are low for over 33 ms, the stuck-bus timer will expire, and the internal i 2 c interface and the sdao pin pull-down logic will be reset to release the bus. normal communication will resume at the next start command. acknowledgethe acknowledge signal is used for handshaking between the master and the slave to indicate that the last byte of data was received. the master always releases the sda line during the acknowledge clock pulse. the ltc2946 will pull the sda line low on the 9 th clock cycle to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master can abort the transmis - sion by generating a stop condition. when the master is receiving data from the slave, the master must acknowledge the slave by pulling down the sda line during the 9 th clock pulse to indicate receipt of a data byte. after the last byte has been received by the master, it will leave the sda line high ( not acknowledge) and issue a stop condition to terminate the transmission.write protocol the master begins a write operation with a start condition followed by the seven-bit slave address and the r/ w bit set to zero. after the addressed ltc2946 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to write. the ltc2946 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. the master then delivers the data byte and the ltc2946 acknowledges once more and writes the data into the internal register pointed to by the register address pointer. if the master continues sending additional data bytes with a write word or extended write command, the additional data bytes will be acknowledged by the ltc2946, the register address pointer will auto - matically increment by one, and data will be written as previously stated. the write operation terminates and the register address pointer resets to 00 h when the master sends a stop condition.read protocol the master begins a read operation with a start condi - tion followed by the 7- bit slave address and the r/w bit set to zero. after the addressed ltc2946 acknowledges applications information downloaded from: http:///
ltc 2946 21 2946fa for more information www.linear.com/ltc2946 applications information the address byte, the master then sends a command byte that indicates which internal register the master wishes to read. the ltc2946 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. the master then sends a repeated start condition followed by the same 7- bit address with the r/w bit now set to 1. the ltc2946 acknowledges and sends the contents of the requested register. the transmission terminates when the master sends a stop condition. if the master acknowledges the transmitted data byte, as in a read word command, the ltc2946 will send the contents of the next register. if the master keeps acknowledging, the ltc2946 will keep incrementing the register address pointer and sending out data bytes. the read operation terminates and the register address pointer resets to 00 h when the master sends a stop condition.alert response protocol when any of the fault bits in the fault1 and fault2 register are set, a bus alert is generated if the appropriate bit in the alert1 or alert2 register has been set and gpio3 is configured as an alert output. this allows the bus master to select which faults will generate alerts. at power-up, both alert registers are cleared ( no alerts enabled) and the gpio 3 ( alert ) pin is high. if an alert is enabled, the corresponding fault causes the gpio3 ( alert ) pin to pull low. the bus master responds to the alert in accordance with the smbus alert response protocol by broadcasting the alert response address 0001_ 100b, and the ltc2946 replies with its own address and re - leases its gpio 3 ( alert ) pin, as shown in figure 14. the gpio 3 ( alert ) line is also released if cb[7] is set and the ltc2946 is addressed ( see table 4) by any message. the gpio 3 ( alert ) signal is not pulled low again until the f lt registers indicate a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults will not generate additional alerts until the associated f lt register bits have been cleared. if two or more ltc2946s on the same bus are generat - ing alerts when the ara is broadcast, the bus master will repeat the alert response protocol until the gpio3 ( alert ) line is released. standard i 2 c arbitration causes the device with the highest priority ( lowest address) to reply first and the device with the lowest priority ( highest address) to reply last.opto-isolating the i 2 c bus opto-isolating a standard i 2 c device is complicated by the bidirectional sda pin. the ltc2946/ltc2946-1 minimize this problem by splitting the standard i 2 c sda line into sdai (input) and sdao ( output, ltc2946) or sdao ( inverted output, ltc2946-1). the scl is an input-only pin and does not require special circuitry to isolate. for conven - tional nonisolated i 2 c applications, use the ltc2946 and tie the sdai and sdao pins together to form a standard i 2 c sda pin. low speed isolated interfaces that use standard open- drain opto-isolators can use the ltc2946 with the sdai and sdao pins separated, as shown in figure 15. connect sdai to the output of the incoming opto-isolator with a pull-up resistor to intv cc or a local 5 v supply; connect sdao to the cathode of the outgoing opto-isolator with a current-limiting resistor in series with the anode. the input and output must be connected together on the isolated side of the bus to allow the ltc2946 to participate in i 2 c arbitration. note that maximum i 2 c bus speed will gener- ally be limited by the speed of the opto-couplers used in this application. the shunt regulators can supply up to 34 ma of current to drive opto-isolator and pull-up resistors, as shown in figure 16 and figure 17. for identical sdai/scl pull-up resistors the maximum load is: i load(max) = v ccz(max) ? 2 r5 + 1 r4 ?? ? ?? ? i load(max) = 6.7v ? 2 r5 + 1 r4 ?? ? ?? ? (2) r shunt can then be calculated using equation 1. note that both ltc2946 and ltc2946-1 can be used in the shunt figure 14. ltc2946 serial bus sda alert response protocol s alert response address 0 0 0 1 1 0 0 device address a7:a0 1 1 r 0 2946 f14 a a p downloaded from: http:///
ltc 2946 22 2946fa for more information www.linear.com/ltc2946 figure 15. opto-isolation of a 10khz i 2 c interface between ltc2946 and microcontroller applications information figure 16. low speed 10khz opto-isolators powered from low side shunt regulator (scl omitted for clarity) figure 17. low speed 10khz opto-isolators powered from high side shunt regulator (scl omitted for clarity) ltc2946 sdai sdao gnd gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m r41k r510k r60.47k r710k v dd r shunt 2946 f16 r sns 0.02 sense C sense + intv cc v dd c2 1f v out v ee v ee ltc2946-1 sdai sdao gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m r41k r510k r61k r710k v dd r shunt v in 2946 f17 r sns 0.02 sense + sense C intv cc v dd c2 1f mocd207m1/2 mocd207m 2946 f15 scl 5v ltc2946 sdai sdao r70.47k r60.82k r80.47k r102k 3.3v v dd gnd p sclsda r510k r410k gnd downloaded from: http:///
ltc 2946 23 2946fa for more information www.linear.com/ltc2946 applications information figure 18. opto-isolation of a 1.5khz i 2 c interface between ltc2946-1 and microcontroller (scl omitted for clarity) figure 19. opto-isolation of a i 2 c interface with low power, high speed opto-couplers (scl omitted for clarity) regulator applications mentioned. figure 18 shows an alternate connection for use with low speed opto-couplers and the ltc2946-1. this circuit uses a limited-current pull-up on the internally clamped sdai pin and clamps the sdao pin with the input diode of the outgoing opto- isolator, removing the need to use intv cc for biasing in the absence of an auxiliary low voltage supply. for proper clamping: v s(max) ? v sda,scl(min) i sda,scl(max) r4 v s(max) ? v sda,scl(max) i sda,scl(min) v s(max) ? 5.9v 5ma r4 v s(max) ? 6.9v 0.5ma (3) as an example, a supply that operates from 36 v to 72 v would require the value of r4 to be between 13 k and 58 k. the ltc2946-1 must be used in this application to ensure that the sdao signal polarity is correct. the ltc2946-1 can also be used with high speed opto- couplers with push-pull outputs and inverted logic as shown in figure 19. the incoming opto-isolator draws power from the intv cc , and the data output is connected directly to the sdai pin with no pull-up required. ensure the current drawn does not exceed the 10 ma maximum capability of the intv cc pin. the sdao pin is connected to the cathode of the outgoing opto-coupler with a current limiting resistor connected back to intv cc . an additional discrete n-channel mosfet is required at the output of the outgoing opto-coupler to provide the open-drain pull- down that the i 2 c bus requires. finally, the input of the incoming opto-isolator is connected back to the output as in the low speed case. ltc2946-1 sdai sdao gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m v in 48v r420k r55.6k r60.47k r72k v dd 2946 f18 v in 48v 1/2 acpl-064l* 1/2 acpl-064l**cmos output iso_sda c 1 1f c2 1f r52k v dd intv cc ltc2946-1 sdao sdai gnd v cc v cc gnd gnd bs170 q1 r62k r72k 2946 f19 3.3v gnd sda p v dd downloaded from: http:///
ltc 2946 24 2946fa for more information www.linear.com/ltc2946 applications information layout considerations a kelvin connection between the sense resistor r sns and the ltc2946 is recommended to achieve accurate current sensing ( figure 20). the recommended minimum trace width for 1 oz copper foil is 0.02 " per amp to ensure the trace stays at a reasonable temperature. using 0.03 " per amp or wider is preferred. note that 1 oz copper exhibits a sheet resistance of about 530? per square. in very high current applications where the sense resistor can dissipate significant power, the pcb layout should include good thermal management techniques such as extra vias and wide metal area. the crystal oscillators clock amplitude is sensitive to parasitics such as stray capacitance on the clkout pin and coupling between the clkin and clkout pins. it is recommended that the clkin and clkout traces from the ltc2946 to the crystal oscillator network be as short as practical with the load capacitors placed next to the crystal, as shown in figure 21. to minimize stray capaci - tances, avoid large ground planes and digital signals near the crystal network. design example given a 20 m sense resistor, calculate the weight value per lsb for the current, power, charge and energy registers: current = 25v/lsb/r sns = 1.25ma/lsb voltage = 25mv/lsb (sense + / v dd is sensing the voltage) power = 1.25ma/lsb ? 25mv/lsb = 31.25w/lsb time = 16.39543ms/lsb (default configuration 250 khz target frequency) charge = 1.25ma/lsb ? 16 ? 16.384ms/lsb = 327.9086c/lsb energy = 31.25 w ? 65536 ? 16.39543ms = 33.578mj/lsb figure 20. recommended layout for kelvin connection figure 21. recommended layout for crystal oscillator v in r sns toload sense + sense C 2946 f20 1615 14 13 12 11 10 9 17 12 3 4 5 6 7 8 14 13 6 11 12 45 15 3 2 1 16 17 8 9 10 7 gnd c4 c3 2946 f21 x1 clkin clkout downloaded from: http:///
ltc 2946 25 2946fa for more information www.linear.com/ltc2946 applications information table 1. ltc2946 device addressing description hex device address binary device address ltc2946 address pins h a6 a5 a4 a3 a2 a1 a0 r/ w adr1 adr0 mass write cc 1 1 0 0 1 1 0 0 x x alert response 19 0 0 0 1 1 0 0 1 x x 0 ce 1 1 0 0 1 1 1 x h l 1 d0 1 1 0 1 0 0 0 x nc h 2 d2 1 1 0 1 0 0 1 x h h 3 d4 1 1 0 1 0 1 0 x nc nc 4 d6 1 1 0 1 0 1 1 x nc l 5 d8 1 1 0 1 1 0 0 x l h 6 da 1 1 0 1 1 0 1 x h nc 7 dc 1 1 0 1 1 1 0 x l nc 8 de 1 1 0 1 1 1 1 x l l table 2. ltc2946 register addresses and contents register addr register name read/write description default 00h ctrla r/w operation control register a 18h 01h ctrlb r/w operation control register b 00h 02h alert1 r/w selects which primary faults generate alerts 00h 03h status1 r primary status information 00h 04h fau lt1 r/w primary fault log 00h 05h power msb2 r/w power msb2 data xxh 06h power msb1 r/w power msb1 data xxh 07h power lsb r/w power lsb data xxh 08h max power msb2 r/w maximum power msb2 data 00h 09h max power msb1 r/w maximum power msb1 data 00h 0ah max power lsb r/w maximum power lsb data 00h 0bh min power msb2 r/w minimum power msb2 data ffh 0ch min power msb1 r/w minimum power msb1 data ffh 0dh min power lsb r/w minimum power lsb data ffh 0eh max power threshold msb2 r/w maximum power threshold msb2 to generate alert ffh 0fh max power threshold msb1 r/w maximum power threshold msb1 to generate alert ffh 10h max power threshold lsb r/w maximum power threshold lsb to generate alert ffh 11h min power threshold msb2 r/w minimum power threshold msb2 to generate alert 00h 12h min power threshold msb1 r/w minimum power threshold msb1 to generate alert 00h 13h min power threshold lsb r/w minimum power threshold lsb to generate alert 00h 14h sense msb r/w sense msb data xxh 15h sense lsb r/w sense lsb data x0h 16h max sense msb r/w maximum sense msb data 00h 17h max sense lsb r/w maximum sense lsb data 00h 18h min sense msb r/w minimum sense msb data ffh 19h min sense lsb r/w minimum sense lsb data f0h 1ah max sense threshold msb r/w maximum sense threshold msb to generate alert ffh downloaded from: http:///
ltc 2946 26 2946fa for more information www.linear.com/ltc2946 applications information 1bh max sense threshold lsb r/w maximum sense threshold lsb to generate alert f0h 1ch min sense threshold msb r/w minimum sense threshold msb to generate alert 00h 1dh min sense threshold lsb r/w minimum sense threshold lsb to generate alert 00h 1eh v in msb r/w adc v in msb data xxh 1fh v in lsb r/w adc v in lsb data x0h 20h max v in msb r/w maximum v in msb data 00h 21h max v in lsb r/w maximum v in lsb data 00h 22h min v in msb r/w minimum v in msb data ffh 23h min v in lsb r/w minimum v in lsb data f0h 24h max v in threshold msb r/w maximum v in threshold msb to generate alert ffh 25h max v in threshold lsb r/w maximum v in threshold lsb to generate alert f0h 26h min v in threshold msb r/w minimum v in threshold msb to generate alert 00h 27h min v in threshold lsb r/w minimum v in threshold lsb to generate alert 00h 28h adin msb r/w adin msb data xxh 29h adin lsb r/w adin lsb data x0h 2ah max adin msb r/w maximum adin msb data 00h 2bh max adin lsb r/w maximum adin lsb data 00h 2ch min adin msb r/w minimum adin msb data ffh 2dh min adin lsb r/w minimum adin lsb data f0h 2eh max adin threshold msb r/w maximum adin threshold msb to generate alert ffh 2fh max adin threshold lsb r/w maximum adin threshold lsb to generate alert f0h 30h min adin threshold msb r/w minimum adin threshold msb to generate alert 00h 31h min adin threshold lsb r/w minimum adin threshold lsb to generate alert 00h 32h alert2 r/w selects which secondary faults generate alerts 00h 33h gpio_cfg r/w gpio configuration 00h 34h time counter msb3 r/w time counter msb data3 xxh 35h time counter msb2 r/w time counter msb data2 xxh 36h time counter msb1 r/w time counter msb data1 xxh 37h time counter lsb r/w time counter lsb data xxh 38h charge msb3 r/w charge msb data3 xxh 39h charge msb2 r/w charge msb data2 xxh 3ah charge msb1 r/w charge msb data1 xxh 3bh charge lsb r/w charge lsb data xxh 3ch energy msb3 r/w energy msb data3 xxh 3dh energy msb2 r/w energy msb data2 xxh 3eh energy msb1 r/w energy msb data1 xxh 3fh energy lsb r/w energy lsb data xxh 40h status2 r secondary status information 00h 41h fau lt2 r/w secondary fault log 00h 42h gpio3_ctrl r/w gpio3 control command 00h 43h clk_div r/w clock divider command 04h e7h mfr_special_ id msb r manufacturer special id msb data 60h e8h mfr_special_id lsb r manufacturer special id lsb data 01h downloaded from: http:///
ltc 2946 27 2946fa for more information www.linear.com/ltc2946 applications information table 3. ctrla register (00h): read/write bit register name operation default ca[7] adin configuration [1] = adin measured with respect to intv cc [0] = adin measured with respect to gnd 0 ca[6:5] offset calibration configuration offset calibration[11] = 1st power-up or use last calibrated result [10] = once every 128 conversions [01] = once every 16 conversions [00] = every conversion 00 ca[4 :3] voltage selection [11] = sense + [10] = adin[01] = v dd [00] = sense** 11 ca[2 :0] channel configuration [111] = snapshot mode (channel defined by ca[4:3]). no power, energy or charge data generated [110] = voltage measurement once followed by current measurement indefinitely* [101] = adin, voltage, current measurement at 1/256, 1/256 and 254/256 duty cycle, respectively* [100] = adin, voltage, current measurement at 1/32, 1/32 and 30/32 duty cycle, respectively* [011] = alternate adin, voltage and current measurement* [010] = voltage, current measurement at 1/128 and 127/128 duty cycle, respectively* [001] = voltage, current measurement at 1/16 and 15/16 duty cycle, respectively* [000] = alternate voltage, current measurement* 000 *voltage defined by ca[4:3] in polling modes. **if sense (00) is selected and the channel configuration is other than snapshot mode (111) the voltage data is always the value in the v in register prior to the mode change. it is recommended that sense be avoided when polling modes are used. table 4. ctrlb register (01h): read/write bit register name operation default cb[7] alert clear enable clear alert if device is addressed by the master [1] = enable[0] = disable 0 cb[6] shutdown [1] = shutdown [0] = power-up 0 cb[5] cleared on read control fault registers cleared on read [1] = cleared on read[0] = registers not affected by reading 0 cb[4] stuck bus timeout auto wake-up allows part to exit shutdown mode when stuck-bus timer is reached [1] = enable[0] = disable 0 cb[3:2] enable accumulation [11] = reserved [10] = follows acc state (gpio2, see table 9) acc high, accumulate acc low, no accumulate [01] = no accumulate [00] = accumulate 00 cb[1:0] auto-reset mode/ reset [11] = reset all registers [10] = reset accumulator (time counter, charge and energy) registers [01] = enable auto-reset [00] = disable auto-reset 00 downloaded from: http:///
ltc 2946 28 2946fa for more information www.linear.com/ltc2946 applications information table 5. alert1 register (02h): read/write bit register name operation default al1[7] maximum power alert enables alert when power > maximum power threshold [1] = enable alert[0] = disable alert 0 al1[6] minimum power alert enables alert when power < minimum power threshold [1] = enable alert[0] = disable alert 0 al1[5] maximum i sense alert enables alert when i sense > maximum i sense threshold [1] = enable alert[0] = disable alert 0 al1[4] minimum i sense alert enables alert when i sense < minimum i sense threshold [1] = enable alert[0] = disable alert 0 al1[3] maximum v in alert enables alert when v in > maximum v in threshold [1] = enable alert[0] = disable alert 0 al1[2] minimum v in alert enables alert when v in < minimum v in threshold [1] = enable alert[0] = disable alert 0 al1[1] maximum adin alert enables alert when adin > maximum adin threshold [1] = enable alert[0] = disable alert 0 al1[0] minimum adin alert enables alert when adin < minimum adin threshold [1] = enable alert[0] = disable alert 0 table 6. status1 register (03h): read bit register name operation default s1[7] power overvalue power > maximum power threshold [1] = power overvalue [0] = power not overvalue 0 s1[6] power undervalue power < minimum power threshold [1] = power undervalue [0] = power not undervalue 0 s1[5] i sense overvalue i sense > maximum i sense threshold [1] = i sense overvalue [0] = i sense not overvalue 0 s1[4] i sense undervalue i sense < minimum i sense threshold [1] = i sense undervalue [0] = i sense not undervalue 0 s1[3] v in overvalue v in > maximum v in threshold [1] = v in overvalue [0] = v in not overvalue 0 s1[2] v in undervalue vin < minimum v in threshold [1] = v in undervalue [0] = v in not undervalue 0 s1[1] adin overvalue adin > maximum adin threshold [1] = adin overvalue [0] = adin not overvalue 0 s1[0] adin undervalue adin < minimum adin threshold [1] = adin undervalue [0] = adin not undervalue 0 downloaded from: http:///
ltc 2946 29 2946fa for more information www.linear.com/ltc2946 applications information table 7. fau lt1 register (04h): read/write bit register name operation default f1[7] power overvalue fault power > maximum power threshold [1] = power overvalue fault occurred [0] = no power overvalue fault occurred 0 f1[6] power undervalue fault power < minimum power threshold [1] = power undervalue fault occurred [0] = no power undervalue fault occurred 0 f1[5] i sense overvalue fault i sense > maximum i sense threshold [1] = i sense overvalue fault occurred [0] = no i sense overvalue fault occurred 0 f1[4] i sense undervalue fault i sense < minimum i sense threshold [1] = i sense undervalue fault occurred [0] = no i sense undervalue fault occurred 0 f1[3] v in overvalue fault vin > maximum v in threshold [1] = v in overvalue fault occurred [0] = no v in overvalue fault occurred 0 f1[2] v in undervalue fault vin < minimum v in threshold [1] = v in undervalue fault occurred [0] = no v in undervalue fault occurred 0 f1[1] adin overvalue fault adin > maximum adin threshold [1] = adin overvalue fault occurred [0] = no adin overvalue fault occurred 0 f1[0] adin undervalue fault adin < minimum adin threshold [1] = adin undervalue fault occurred [0] = no adin undervalue fault occurred 0 table 8. alert2 register (32h): read/write bit register name operation default al2[7] adc conversion done alert alert when adc finishes a conversion [1] = enable[0] = disable 0 al2[6] gpio1 input alert alert if gpio1 is low when gp[7:6] = [01] (gpio1 input active low), orgpio1 is high when gp[7:6] = [00] (gpio1 input active high) [1] = enable alert [0] = disable alert 0 al2[5] gpio2 input alert alert if gpio2 is low when gp[5:4] = [01] (gpio2 input active low), orgpio2 is high when gp[5:4] = [00] (gpio2 input active high) [1] = enable alert [0] = disable alert 0 al2[4] reserved 0 al2[3] stuck-bus timeout wake-up alert alert if part exits shutdown mode after stuck-bus timer expires with cb[4] = 1 [1] = enable alert[0] = disable alert 0 al2[2] energy overflow alert alert if energy register overflow [1] = enable alert[0] = disable alert 0 downloaded from: http:///
ltc 2946 30 2946fa for more information www.linear.com/ltc2946 applications information al2[1] charge overflow alert alert if charge register overflow [1] = enable alert[0] = disable alert 0 al2[0] time counter overflow alert alert if time counter register overflow [1] = enable alert[0] = disable alert 0 table 9. gpio_cfg register (33h): read/write bit register name operation default gp[7:6] gpio1 configure [11] = general purpose input, active high [10] = general purpose input, active low[01] = general purpose output, hi-z [00] = general purpose output, pulls low 00 gp[5:4] gpio2 configure [11] = general purpose input, active high [10] = general purpose input, active low[01] = general purpose output, gpio = gp[1] [00] = accumulate input 00 gp[3:2] gpio3 configure [11] = general purpose input, active high [10] = general purpose input, active low [01] = general purpose output, see register 42h (table 12) [00] = alert output 00 gp[1] gpio2 output [1] = pulls low [0] = hi-z 0 gp[0] reserved 0 downloaded from: http:///
ltc 2946 31 2946fa for more information www.linear.com/ltc2946 applications information table 10. status2 register (40h): read bit name operation default s2[7] reserved 0 s2[6] gpio1 state gp[7] gp[6] function gpio state 1 0 gpio1 input = active low [1] = gpio1 low [0] = gpio1 high 1 1 gpio1 input = active high [1] = gpio1 high [0] = gpio1 low 0 s2[5] gpio2 state gp[5] gp[4] function gpio state 0 0 gpio2 input = acc [1] = acc high [0] = acc low 1 0 gpio2 input = active low [1] = gpio2 low [0] = gpio2 high 1 1 gpio2 input = active high [1] = gpio2 high [0] = gpio2 low 0 s2[4] gpio3 state gp[3] gp[2] function gpio state 1 0 gpio3 input = active low [1] = gpio3 low [0] = gpio3 high 1 1 gpio3 input = active high [1] = gpio3 high [0] = gpio3 low 0 s2[3] adc busy in snapshot mode 0 s2[2] energy register overflow energy register overflow [1] = energy register overflow [0] = energy register not overflow 0 s2[1] charge register overflow charge register overflow [1] = charge register overflow [0] = charge register not overflow 0 s2[0] time counter register overflow time counter register overflow [1] = time counter register overflow [0] = time counter register not overflow 0 downloaded from: http:///
ltc 2946 32 2946fa for more information www.linear.com/ltc2946 table 11. fau lt2 register (41h): read/write bit register name operation default f2[7] reserved 1 f2[6] gpio1 input fault indicates gpio1 was at active level as a general purpose input [1] = gpio1 input was active [0] = gpio1 input was inactive 0 f2[5] gpio2 input fault indicates gpio2 was at active level as a general purpose input [1] = gpio2 input was active [0] = gpio2 input was inactive 0 f2[4] gpio3 input fault indicates gpio3 was at active level as a general purpose input [1] = gpio3 input was active [0] = gpio3 input was inactive 0 f2[3] stuck-bus timeout wake-up fault with cb[4] = 1 [1] = part exited shutdown mode after stuck-bus timer expired [0] = no stuck bus timeout wake-up fault occurred 0 f2[2] energy register overflow fault energy register overflow [1] = energy register overflow fault [0] = no energy overflow fault 0 f2[1] charge register overflow fault charge register overflow [1] = charge register overflow fault [0] = no charge overflow fault 0 f2[0] time counter register overflow fault time counter register over flow [1] = time counter register overflow fault [0] = no time counter overflow fault 0 table 12. gpio3_ctrl register (42h): read/write bit register name operation default gc[7] alert generated if gpio3 is configured as alert output, it pulls low when alert is generated. otherwise, this bit does not have an effect on gpio3. this bit is set when an alert is generated or a 1 is written. to clear this bit, write 0 via i 2 c. 0 gc[6] gpio3 pull-down control controls gpio3 as a general purpose output [1] = gpio3 pulls low[0] = gpio3 hi-z this bit does not have effect on gpio3 if it is configured otherwise. 0 gc[5:0] reserved read only 00000b table 13. clk_div register (43h): read/write bit register name operation default cd[7:5] reserved read only 000b cd[4:0] clock divider integer input clock frequency at clkin is divided by 4 of this integer to produce the target 250khz system clock. 00100b applications information downloaded from: http:///
ltc 2946 33 2946fa for more information www.linear.com/ltc2946 table 14. register data format: read/write register bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) adc, min/max adc, min/max adc threshold msb data (11) data (10) data (9) data (8) data (7) data (6) data (5) data (4) adc, min/max adc, min/max adc threshold lsb data (3) data (2) data (1) data (0) read as 0 read as 0 read as 0 read as 0 power, min/max power, min/max power threshold msb2 data (23) data (22) data (21) data (20) data (19) data (18) data (17) data (16) power, min/max power, min/max power threshold msb1 data (15) data (14) data (13) data (12) data (11) data (10) data (9) data (8) power, min/max power, min/max power threshold lsb data (7) data (6) data (5) data (4) data (3) data (2) data (1) data (0) time counter, charge, energy msb3 data (31) data (30) data (29) data (28) data (27) data (26) data (25) data (24) time counter, charge, energy msb2 data (23) data (22) data (21) data (20) data (19) data (18) data (17) data (16) time counter, charge, energy msb1 data (15) data (14) data (13) data (12) data (11) data (10) data (9) data (8) time counter, charge, energy lsb data (7) data (6) data (5) data (4) data (3) data (2) data (1) data (0) mfr_special_id msb data (15) data (14) data (13) data (12) data (11) data (10) data (9) data (8) mfr_special_id lsb data (7) data (6) data (5) data (4) data (3) data (2) data (1) data (0) applications information table 15. time per lsb of timer register ca[6:5] see table 3 ca[2:0] see table 3 n xx 110 4098.5 11 011 4099.75 010, 101 4098.5098 001, 100 4098.5806 000 4099.3333 10 011 4099.7355 010, 101 4098.5097 001, 100 4098.5800 000 4099.3549 01 011 4099.6429 010, 101 4098.5092 001, 100 4098.5758 000 4099.2692 00 011 4099 010, 101 4098.5049 001, 100 4098.5397 000 4098.8571 time /lsb = n ? 4 ?clk _div f clkin or n ? 4s if internal clock used. downloaded from: http:///
ltc 2946 34 2946fa for more information www.linear.com/ltc2946 typical applications power, charge and energy monitoring in ?48v system using low side sensing (1.5khz i 2 c interface) v ee v ee v ee c1 1f mocd207mmocd207m nc = no connect 2946 ta03 adr0 adr1 adin scl v dd intv cc sdai sdao gpio3 alert sense C gnd sense + ltc2946 v ee C48v input r70.47k r31k C48v rtn r41k v out ca[4:3] = 01, see table 3 r80.47k r910k r1010k r1110k 3.3v r sns 0.02 v dd gnd p sclsda int r120k r220k nc gpio1 gpio2 clkin clkout r612.1k r1212.1k r5681k c2 0.1f bidirectional power monitor with energy and charge monitor in forward path c2 0.1f c333pf v in 2.7v to 5.8v r sns 0.2 v out 0.5a gp output r1 2k r2 2k r3 2k 3.3v v dd sclsda int gnd adr0 scl v dd intv cc sdai sdao gpio1 alert adr1 sense + accumulate sense C ltc2946 p gpio3 clkout gndgpio2 r42k 3.3v clkin 2946 ta10 adin c433pf x1: abls-4.000mhz-b2-t power for reverse path = code adin code vdd to be performed by p ca[7] = 1, see table 3 x1 downloaded from: http:///
ltc 2946 35 2946fa for more information www.linear.com/ltc2946 typical applications dual power, charge and energy monitor using single opto-coupler for galvanic isolation and blocking diodes for data retention when either supply fails c2 0.1f scl v dd v out1 v in1 24v intv cc sdai gnd ltc2946 r53.9 sdao gpio2gpio3 gpio1 gp02a gp01a adr1 adr0 adin sense + sense C r sns1 0.02 c1 1f d1 bat54 v cc gnd hcpl-063l hcpl-063l 2946 ta07 c3 0.1f scl v dd v out2 keep short! v in2 48v intv cc sdai gnd ltc2946 r133.2k r218.2k sdao gpio2 gpio3gpio1 gp02bnc gp01b adr1adr0 adin sense + sense C r sns2 0.02 c4 1f d2 bat54 v cc gnd r80.47k r90.47k r1010k r1110k r1210k 3.3v 3.3v v dd gnd p sclsda x1 int r31k r41k alert c40.22f x1: abls-4.000mhz-b2-t r71k r61k c533pf v 5vgen clkout clkin c633pf clkout clkin gpo1a, gpo2a, gpo1b and gpo2b are controlled by microprocessor writing commands to ltc2946s via i 2 c v in2 v 5vgen r1810k red gp02b red: v in2 overload r17100k v in2 v 5vgen r1610k green gpo1b green: v in2 ok r15100k v in1 v 5vgen r144.7k red gpo2a red: v in1 overload r13100k v in1 v 5vgen v 5vgen r64.7k green gpo1a green: v in1 ok r5100k downloaded from: http:///
ltc 2946 36 2946fa for more information www.linear.com/ltc2946 v cc gnd r shunt 2 5k in series c1 1f hcpl-063l v ee v ee hcpl-063l 2946 ta05 adr0 adr1 scl v dd intv cc fan on output temp monitor input sdai sdao adin sense C gnd sense + ltc2946 c3, 33pfc4, 33pf v cc gnd C48v rtn v ee C48v input r70.47k r21k r11k v out c2 1f r80.47k r91k r101k r1110k 3.3v 3.3v r sns 0.02 v dd gnd p sclsda int r12 100 q1 pzta42 d1 1n4148ws r41k r30.47k r5732k r615k gpio3 clkout gpio1gpio2 clkin alert x1: abls-4.000mhz-b2-t ca[4:3] = 10, see table 3 x1 typical applications power, charge and energy monitor in ?48v harsh environment using intv cc shunt regulator to tolerate 200v transients power, charge and energy monitor for main supply and power monitor for secondary supply with single ltc2946 c2 0.1f v in1 0v to 100v v in2 2.7v to 5.8v ca[7] = 1, see table 3 power for secondary supply = code adin code vdd . to be performed by p v out2 0.5a (8-bit) v out1 5a r sns1 0.02 nc gp output r1 2k r2 2k r3 2k 3.3v v dd sclsda int gnd adr1 scl adr0v dd gnd sdai sdao gpio1 alert sense + accumulate sense C ltc2946 p gpio3 clkout gpio2 r42k 3.3v clkin 2946 ta06 intv cc adin r sns 0.25 downloaded from: http:///
ltc 2946 37 2946fa for more information www.linear.com/ltc2946 typical applications 6v to 300v high side power, charge and energy monitor v cc gnd c1 0.1f acpl-064l ca[7] = 1, ca[4:3] = 10, see table 3 * ddz9689, diodes, inc. fgnd fgnd acpl-064l 2946 ta07 gpio1 scl v dd intv cc sdai sdao gpio2 gnd ltc2946-1 v cc gnd r70.47k c2 1f r80.47k r91k m2bs170 r101k 3.3v 3.3v v dd gnd p sclsda int q12n3904 q2mmbt6520l r42k r32k r15.1k r2750k gpio3 adr1 adr0 clkin adinclkout alert fgnd z1*5.1v q32n3904 m1bsp135 r610k r11100 r510k m3bsp135 v in v out sense + sense C r sns 0.02 downloaded from: http:///
ltc 2946 38 2946fa for more information www.linear.com/ltc2946 typical applications 12v, 50a power, charge and energy monitor wide range ?4v to ?500v negative power, charge and energy monitor (10khz i 2 c interface) v ee v ee c2 0.1f mocd207mmocd207m 2946 ta09 adr0 adr1 adin scl v dd intv cc sdai sdao gpio3 alert sense C gnd sense + ltc2946 c1 0.1f v ee r70.47k r31k r13 10k m1bsp135 r41k v out r80.47k r910k r1010k r1110k 3.3v r sns 0.02 v dd gnd p sclsda int r12k r22k r126.04k r6750k z14.7v r5750k rtn gpio1 gpio2 clkin clkout ca[4:3] = 10, see table 3 c2 0.1f c30.22f v in 12v r sns 0.002, 5w v out 50a v adin nc gp output r1 2k r2 2k r3 2k 3.3v v dd sclsda int gnd adr0 scl v dd intv cc sdai sdao gpio1 alert adr1 sense + accumulate sense C ltc2946 p gpio3 clkout gndgpio2 r42k 3.3v clkin 2946 ta08 adin divb out v + v + gnd gnd ltc6930-8.00 diva divc downloaded from: http:///
ltc 2946 39 2946fa for more information www.linear.com/ltc2946 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note:1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de16) dfn 0806 rev ? pin 1 notchr = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 packageoutline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) downloaded from: http:///
ltc 2946 40 2946fa for more information www.linear.com/ltc2946 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.10 (.201) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev a) downloaded from: http:///
ltc 2946 41 2946fa for more information www.linear.com/ltc2946 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 03/15 changed y-axis of typical applications graph. corrected i sense(lo) C conditions. corrected r shunt equation. 14 16 downloaded from: http:///
ltc 2946 42 2946fa for more information www.linear.com/ltc2946 ? linear technology corporation 2014 lt 0315 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2946 typical application related parts part number description comments lt ? 2940 power and current monitor 4-quadrant multiplication, 5% power accuracy, 4v to 80v operation ltc2941 i 2 c battery gas gauge 2.7v to 5.5v operation, 1% charge accuracy ltc2942 i 2 c battery gas gauge 2.7v to 5.5v operation, 1% charge, voltage and temperature ltc2943 high voltage battery gas gauge 3.6v to 20v operation, 1% charge, voltage, current and temperature ltc2945 wide range i 2 c power monitor 0v to 80v operation, 12-bit adc with 0.75% tue ltc2990 quad i 2 c temperature, voltage and current monitor 3v to 5.5v operation, 14-bit adc ltc4150 coulomb counter/battery gas gauge 2.7v to 8.5v operation, voltage-to-frequency converter ltc4151 high voltage i 2 c current and voltage monitor 7v to 80v operation, 12-bit resolution with 1.25% tue ltc4215 single channel, hot swap? controller with i 2 c monitoring 8-bit adc, adjustable current limit and inrush, 2.9v to 15v operation ltc4222 dual channel, hot swap controller with i 2 c monitoring 10-bit adc, adjustable current limit and inrush, 2.9v to 29v operation ltc4260 positive high voltage hot swap controller with i 2 c monitoring 8-bit adc, adjustable current limit and inrush, 8.5v to 80v operation ltc4261 negative high voltage hot swap controller with i 2 c monitoring 10-bit adc, floating topology, adjustable inrush rail-to-rail power, charge and energy monitor 2.7v to 5.8v c2 0.1f c333pf x1 x1: abls-4.000mhz-b2-t v in 0v to 100v r sns 0.02 v out v adin gp output r1 2k r2 2k r3 2k 3.3v v dd sclsda int gnd adr0 scl v dd intv cc sdai sdao gpio1 alert adr1 sense + accumulate sense C ltc2946 p gpio3 clkout gndgpio2 r42k 3.3v clkin 2946 ta02 adin c433pf downloaded from: http:///

▲Up To Search▲

Price & Availability of LTC2946HDETRPBF

	To Download LTC2946HDETRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .